Verilog Free Simulator and Viewer

Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well.
Dinotrace : Freeware VCD viewer from veritools

I have tested above combination on linux. Both works fine...and is good to start with.

Sample Design:
^^^^^^^^^^^^
//-----------------------------------------------------
module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end
endmodule

TestBench:
`timescale 1ns/1ps
`include "encoder_using_if.v"
module encoder_test;
wire [3:0] binary_out;
reg enable;
reg [15:0] encoder_in;

encoder_using_if encode(.binary_out (binary_out), .encoder_in (encoder_in) , .enable (enable));

initial begin
#1 enable = 0;
encoder_in = 16'h0;

#2 enable = 1;
encoder_in = 16'h0001;

#3
encoder_in = 16'h0010;
#1 $finish;
end
initial begin
$monitor("Encoder out = %h \n",binary_out);
end
//always @ (enable or encoder_in)
initial
begin
$dumpfile( "foo.vcd" );
$dumpvars( 0, encoder_test );
end
endmodule

Command Used:
^^^^^^^^^^^^^

iverilog testbench.v
./a.out
./dinotrace foo.vcd

Keywords: Verilog, free simulator, waveform viewer, Icarus Verilog, Dinotrace