The 2007 Verification Census

1. Verilog Vs VHDL

2005 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################## 59%
mixed : ################### 38%
VHDL only : # 3%

Now here's the 2007 data with the break out of that vague "mixed" term:

2007 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################ 55.3%
mostly Verilog : ######### 18.0%
both equally : ### 6.5%
mostly VHDL : ######## 16.4%
VHDL only : ## 4.0%

Clearly Verilog is the winner and VHDL is used only military project or for legacy reasons.

2. Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
2005 - "Whose Verilog or VHDL simulator(s) do you currenty use?"

Cadence NC-Sim : ########################### 27%
NC-Verilog : ##################### 21%
Verilog-XL : ## 2%
NC-VHDL : # 1%

Synopsys VCS : ########################################### 43%
VCS-MX : #### 4%

Mentor ModelSim : ################################### 35%

Aldec : ### 3%
Icarus : .5%
Veriwell : .5%
SimuCAD Silos-III : .5%
Finsim : .5%

Here's the new 2007 mindshare data:

2007 - "Whose Verilog or VHDL simulator(s) do you currenty use?"

Cadence NC-Sim : ######################## 24.3%
NC-Verilog : ################## 18.0%
Verilog-XL : # 0.7%
NC-VHDL : # 1.1%

Synopsys VCS : ############################################# 44.7%
VCS-MX : ######### 8.5%

Mentor ModelSim : ################################### 35.3%

Aldec : ### 2.8%
Icarus : .4%
Veripool Verilator : # .6%
SimuCAD Silos-III : 0%
Finsim : 0%

For 2007, Cadence came in second with a 24.3 + 18 + 0.7 + 1.1 = 44.1% total
Verilog/VHDL mindshare. Synopsys took the lead with a 44.7 + 8.5 = 53.2%
total mindshare.

Few Interesting Comments :
Mentor Modelsim. We do do some mixed verilog/vhdl sim's but these
are usually forced on us by IP models only being availble in
Verilog. We currently design using vhdl but are starting to think
about jumping to System Verilog.

- Jeremy Ellis of Ericsson


Synopsys VCS-MX. Mixed, because design is traditionally in VHDL,
IP sometimes in Verilog, testbench in System Verilog.

- [ An Anon Engineer ]


Cadence Incisive 80%, Synopsys VCS 15%, Synopsys VCS-MX (for VHDL
due to acquired IP) 5% currently, emphasis shifting to VCS due to
better System Verilog support.

- [ An Anon Engineer ]


Principally Synopsys VCS.

We tried to keep the code building with Cadence NC-Sim too, but there
were too many differences in scope of System Verilog support to
maintain this for the entire code base (at the time we looked - may
have improved now) - some people use NC-Sim for module test though.

- [ An Anon Engineer ]


Our group is all Verilog. We use Cadence NC Verilog. We are looking
at switching to VCS because their simulator offers more support for
System Verilog.

- [ An Anon Engineer ]


Were currently using a mixture of Synopsys VCS (for unit-level) and
Cadence Incisive (for system-level). We do run mixed simulations
because of IP coming from an internal European group which was using
VHDL at the time they were acquired.

- Kelly Larson of Analog Devices


3:Atrenta Spyglass, Synopsys Leda, Cadence HAL, 0-In CheckList
2007 - "Which linter/coverage tool(s) do you use? Atrenta SpyGlass,
Cadence HAL, Synopsys Leda, Mentor DesignAnalyst, TransEDA or
do you use only the built-in linter/coverage in Synopsys VCS,
Cadence NC-Sim, Mentor ModelSim, Aldec? Please be specific."

Cadence built-in : ######################## 24.0%
Cadence HAL : ########### 11.3%
Verisity : ## 2.0%

Synopsys built-in : ############################ 28.2%
Synopsys LEDA : ##################### 20.8%

Mentor MTI built-in : ####################### 23.0%
Mentor DesignAnalyst : ## 1.9%
0-In CheckList : ## 1.6%

Aldec built-in : ## 2.4%

Atrenta Spyglass : ########################## 25.9%

Novas nLint : ### 2.7%
TransEDA : ## 2.2%
Certess Certitude : # 1.1%
Axiom : # 0.8%

homegrown : ## 1.9%

It must not be that bad, though, for the Atrenta Spyglass folks because if
you look at their 2005 mindshare numbers and the 2007 numbers:

Atrenta Spyglass 2005 : ################## 18.0%

Atrenta Spyglass 2007 : ########################## 25.9%

4.Novas Debussy & Verdi, Veritools UnderTow, DAI SignalScan

"What waveform/debug tools do you use? Veritools Undertow or
Novas DeBussy & nSchema & Verdi vs. only the waveform/debug
built-into Cadence, Synopsys, Mentor, Aldec? Be specific."

Cadence built-in debug : ############################## 29.6%
Cadence DAI SignalScan : ## 1.7%

Synopsys built-in debug : ################################# 33.2%

Mentor MTI built-in debug : ########################## 26.3%

Aldec built-in debug : ### 2.5%

Novas Debussy : ################################# 33.1%
Novas Verdi : ##################### 20.8%
Novas nSchema : ##### 4.5%
Novas nWave : # 1.3%
Novas Siloti : 0.3%

Veritools UnderTow : ### 2.8%
Bybell GTKwave : # 0.8%
Veripool Dinotrace : # 0.6%
Axiom built-in debug : # 0.8%

5:Cadence Verisity Specman "e" vs. Synopsys Vera

2005 - "What do you think about Verisity Specman 'e' vs. Synopsys
Vera? Does your project use either of these?"

don't use : ################################# 43%
Verisity Specman "e" : ###################### 29%
Synopsys Vera : ##################### 27%
we use both : # 1%

And now here's the newer 2007 stats:

2007 - "Does your project use either Cadence Verisity Specman "e" or
Synopsys Vera? (Yes/No) If yes, which one?"

don't use : ############################################ 57.1%
Verisity Specman "e" : ############## 18.2%
Synopsys Vera : ################ 20.7%
we use both : ### 3.9%

Yup, you're seeing that right. All forms of Vera and "e" use has noticeably
dropped in the past 2 years. The "don't use" responses have vividly jumped
from a 43% minority of projects in 2005 to a 57.1% majority of projects in
2007. This is the demise that was being openly talked about back in 2005.

2005 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"

Dead : ####################################### 78%

Growing : ########### 22%


2007 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"


Dead : ######################################### 81.7%

Growing : ######### 18.3%

From the comments, it seems System Verilog (and to a lessor degree) SystemC
use is finally now taking that long predicted bite out of Vera and "e". And
even as a shrinking minority, I did notice a number of fanatical Specman "e"
users who were still very enthusiastic about their language. Vera didn't
seem to have such fanatics -- instead, its users seemed to be OK just giving
in to the big, aggressive Synopsys/Mentor/ARM System Verilog marketing push.

Courtesy : deepchip.com (Checkout the site for detail description, only abstract /interesting points printed here)

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