Tech Funda of the Day

The 2007 Verification Census

2007-04-25T23:47:00.000-07:00

1. Verilog Vs VHDL

2005 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################## 59%
mixed : ################### 38%
VHDL only : # 3%

Now here's the 2007 data with the break out of that vague "mixed" term:

2007 - "Does your project do mixed Verilog/VHDL simulations?"

Verilog only : ############################ 55.3%
mostly Verilog : ######### 18.0%
both equally : ### 6.5%
mostly VHDL : ######## 16.4%
VHDL only : ## 4.0%

Clearly Verilog is the winner and VHDL is used only military project or for legacy reasons.

2. Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
2005 - "Whose Verilog or VHDL simulator(s) do you currenty use?"

Cadence NC-Sim : ########################### 27%
NC-Verilog : ##################### 21%
Verilog-XL : ## 2%
NC-VHDL : # 1%

Synopsys VCS : ########################################### 43%
VCS-MX : #### 4%

Mentor ModelSim : ################################### 35%

Aldec : ### 3%
Icarus : .5%
Veriwell : .5%
SimuCAD Silos-III : .5%
Finsim : .5%

Here's the new 2007 mindshare data:

2007 - "Whose Verilog or VHDL simulator(s) do you currenty use?"

Cadence NC-Sim : ######################## 24.3%
NC-Verilog : ################## 18.0%
Verilog-XL : # 0.7%
NC-VHDL : # 1.1%

Synopsys VCS : ############################################# 44.7%
VCS-MX : ######### 8.5%

Mentor ModelSim : ################################### 35.3%

Aldec : ### 2.8%
Icarus : .4%
Veripool Verilator : # .6%
SimuCAD Silos-III : 0%
Finsim : 0%

For 2007, Cadence came in second with a 24.3 + 18 + 0.7 + 1.1 = 44.1% total
Verilog/VHDL mindshare. Synopsys took the lead with a 44.7 + 8.5 = 53.2%
total mindshare.

Few Interesting Comments :
Mentor Modelsim. We do do some mixed verilog/vhdl sim's but these
are usually forced on us by IP models only being availble in
Verilog. We currently design using vhdl but are starting to think
about jumping to System Verilog.

- Jeremy Ellis of Ericsson

Synopsys VCS-MX. Mixed, because design is traditionally in VHDL,
IP sometimes in Verilog, testbench in System Verilog.

- [ An Anon Engineer ]

Cadence Incisive 80%, Synopsys VCS 15%, Synopsys VCS-MX (for VHDL
due to acquired IP) 5% currently, emphasis shifting to VCS due to
better System Verilog support.

- [ An Anon Engineer ]

Principally Synopsys VCS.

We tried to keep the code building with Cadence NC-Sim too, but there
were too many differences in scope of System Verilog support to
maintain this for the entire code base (at the time we looked - may
have improved now) - some people use NC-Sim for module test though.

- [ An Anon Engineer ]

Our group is all Verilog. We use Cadence NC Verilog. We are looking
at switching to VCS because their simulator offers more support for
System Verilog.

- [ An Anon Engineer ]

Were currently using a mixture of Synopsys VCS (for unit-level) and
Cadence Incisive (for system-level). We do run mixed simulations
because of IP coming from an internal European group which was using
VHDL at the time they were acquired.

- Kelly Larson of Analog Devices

3:Atrenta Spyglass, Synopsys Leda, Cadence HAL, 0-In CheckList
2007 - "Which linter/coverage tool(s) do you use? Atrenta SpyGlass,
Cadence HAL, Synopsys Leda, Mentor DesignAnalyst, TransEDA or
do you use only the built-in linter/coverage in Synopsys VCS,
Cadence NC-Sim, Mentor ModelSim, Aldec? Please be specific."

Cadence built-in : ######################## 24.0%
Cadence HAL : ########### 11.3%
Verisity : ## 2.0%

Synopsys built-in : ############################ 28.2%
Synopsys LEDA : ##################### 20.8%

Mentor MTI built-in : ####################### 23.0%
Mentor DesignAnalyst : ## 1.9%
0-In CheckList : ## 1.6%

Aldec built-in : ## 2.4%

Atrenta Spyglass : ########################## 25.9%

Novas nLint : ### 2.7%
TransEDA : ## 2.2%
Certess Certitude : # 1.1%
Axiom : # 0.8%

homegrown : ## 1.9%

It must not be that bad, though, for the Atrenta Spyglass folks because if
you look at their 2005 mindshare numbers and the 2007 numbers:

Atrenta Spyglass 2005 : ################## 18.0%

Atrenta Spyglass 2007 : ########################## 25.9%

4.Novas Debussy & Verdi, Veritools UnderTow, DAI SignalScan

"What waveform/debug tools do you use? Veritools Undertow or
Novas DeBussy & nSchema & Verdi vs. only the waveform/debug
built-into Cadence, Synopsys, Mentor, Aldec? Be specific."

Cadence built-in debug : ############################## 29.6%
Cadence DAI SignalScan : ## 1.7%

Synopsys built-in debug : ################################# 33.2%

Mentor MTI built-in debug : ########################## 26.3%

Aldec built-in debug : ### 2.5%

Novas Debussy : ################################# 33.1%
Novas Verdi : ##################### 20.8%
Novas nSchema : ##### 4.5%
Novas nWave : # 1.3%
Novas Siloti : 0.3%

Veritools UnderTow : ### 2.8%
Bybell GTKwave : # 0.8%
Veripool Dinotrace : # 0.6%
Axiom built-in debug : # 0.8%

5:Cadence Verisity Specman "e" vs. Synopsys Vera

2005 - "What do you think about Verisity Specman 'e' vs. Synopsys
Vera? Does your project use either of these?"

don't use : ################################# 43%
Verisity Specman "e" : ###################### 29%
Synopsys Vera : ##################### 27%
we use both : # 1%

And now here's the newer 2007 stats:

2007 - "Does your project use either Cadence Verisity Specman "e" or
Synopsys Vera? (Yes/No) If yes, which one?"

don't use : ############################################ 57.1%
Verisity Specman "e" : ############## 18.2%
Synopsys Vera : ################ 20.7%
we use both : ### 3.9%

Yup, you're seeing that right. All forms of Vera and "e" use has noticeably
dropped in the past 2 years. The "don't use" responses have vividly jumped
from a 43% minority of projects in 2005 to a 57.1% majority of projects in
2007. This is the demise that was being openly talked about back in 2005.

2005 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"

Dead : ####################################### 78%

Growing : ########### 22%

2007 - "Where do you think specialty functional verification languages
like Specman "e" and Vera be in 5 years? (Choose one): Dead
or an ever growing part of the chip verification process?"

Dead : ######################################### 81.7%

Growing : ######### 18.3%

From the comments, it seems System Verilog (and to a lessor degree) SystemC
use is finally now taking that long predicted bite out of Vera and "e". And
even as a shrinking minority, I did notice a number of fanatical Specman "e"
users who were still very enthusiastic about their language. Vera didn't
seem to have such fanatics -- instead, its users seemed to be OK just giving
in to the big, aggressive Synopsys/Mentor/ARM System Verilog marketing push.

Courtesy : deepchip.com (Checkout the site for detail description, only abstract /interesting points printed here)

Backspace in Xterm

2007-04-25T00:15:00.000-07:00

If you're using xterm and hitting the backspace key doesn't do what you expect, add this to your .Xdefaults file:

xterm.*.backarrowKey: false

OR add following to .Xdefaults file:

XTerm.VT100.Translations: #override \
Key BackSpace: string(0x7F)\n\
Key Delete: string("\033[3~")\n\
Key Home: string("\033[1~")\n\
Key End: string("\033[4~")

*put Key word inside <>
Keywords: Xterm, backspace, Delete

Verilog in 1 day !!!!

2007-01-31T01:19:00.000-08:00

1. Introduction

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a language used to describe a digital system, for example, a computer or a component of a computer. One may describe a digital system at several levels. For example, an HDL might describe the layout of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i. e., the switch level. Or, it might describe the logical gates and flip flops in a digital system, i. e., the gate level. An even higher level describes the registers and the transfers of vectors of information between registers. This is called the Register Transfer Level (RTL). Verilog supports all of these levels. However, this handout focuses on only the portions of Verilog which support the RTL level.

1.1 What is Verilog?

Verilog is one of the two major Hardware Description Languages (HDL) used by hardware designers in industry and academia. VHDL is the other one. The industry is currently split on which is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware designer puts it, "I hope the competition uses VHDL." VHDL was made an IEEE Standard in 1987, while Verilog is still in the IEEE standardization process. Verilog is very C-like and liked by electrical and computer engineers as most learn the C language in college. VHDL is very Ada-like and most engineers have no experience with Ada.

Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence Design Systems, Inc.'s Systems Division. Until May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a proprietary language of Cadence. Cadence was motivated to open the language to the Public Domain with the expectation that the market for Verilog HDL-related software products would grow more rapidly with broader acceptance of the language. Cadence realized that Verilog HDL users wanted other software and service companies to embrace the language and develop Verilog-supported design tools.

Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at the architectural or behavioral level as well as the lower implementation levels (i. e. , gate and switch levels) leading to Very Large Scale Integration (VLSI) Integrated Circuits (IC) layouts and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must commit to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of Verilog HDL at the architectural or behavioral levels. The handout emphasizes design at the Register Transfer Level (RTL).

1.2 What is VeriWell?

VeriWell is a comprehensive implementation of Verilog HDL from Wellspring Solutions, Inc. VeriWell supports the Verilog language as specified by the OVI language Reference Manual. VeriWell was first introduced in December, 1992, and was written to be compatible with both the OVI standard and with Cadence's Verilog-XL.

Wellspring offers free versions of their VeriWell product available from ftp://iii.net/pub/pub-site/wellspring. Wellspring offers free versions for DOS, Sparc and Linux. The free versions are the same as the industrial versions except they are restricted to a maximum of 1000 lines of HDL code.

1.3 Why Use Verilog HDL?

Digital systems are highly complex. At their most detailed level, they may consists of millions of elements, i. e., transistors or logic gates. Therefore, for large digital systems, gate-level design is dead. For many decades, logic schematics served as the lingua franca of logic design, but not any more. Today, hardware complexity has grown to such a degree that a schematic with logic gates is almost useless as it shows only a web of connectivity and not the functionality of design. Since the 1970s, Computer engineers and electrical engineers have moved toward hardware description languages (HDLs). The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is the top HDL used by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple Computer and Motorola. Industrial designers like Verilog. It works.

The Verilog language provides the digital designer with a means of describing a digital system at a wide range of levels of abstraction, and, at the same time, provides access to computer-aided design tools to aid in the design process at these levels.

Verilog allows hardware designers to express their design with behavioral constructs, deterring the details of implementation to a later stage of design in the design. An abstract representation helps the designer explore architectural alternatives through simulations and to detect design bottlenecks before detailed design begins.

Though the behavioral level of Verilog is a high level description of a digital system, it is still a precise notation. Computer aided design tools, i. e., programs, exist which will "compile" programs in the Verilog notation to the level of circuits consisting of logic gates and flip flops. One could then go to the lab and wire up the logical circuits and have a functioning system. And, other tools can "compile" programs in Verilog notation to a description of the integrated circuit masks for very large scale integration (VLSI). Therefore, with the proper automated tools, one can create a VLSI description of a design in Verilog and send the VLSI description via electronic mail to a silicon foundry in California and receive the integrated chip in a few weeks by way of snail mail. Verilog also allows the designer to specific designs at the logical gate level using gate constructs and the transistor level using switch constructs.

Our goal in the course is not to create VLSI chips but to use Verilog to precisely describe the functionality of any digital system, for example, a computer. However, a VLSI chip designed by way of Verilog's behavioral constructs will be rather slow and be wasteful of chip area. The lower levels in Verilog allow engineers to optimize the logical circuits and VLSI layouts to maximize speed and minimize area of the VLSI chip.

2. The Verilog Language

There is no attempt in this handout to describe the complete Verilog language. It describes only the portions of the language needed to allow students to explore the architectural aspects of computers. In fact, this handout covers only a small fraction of the language. For the complete description of the Verilog HDL, consult the references at the end of the handout.

We begin our study of the Verilog language by looking at a simple Verilog program. Looking at the assignment statements, we notice that the language is very C-like. Comments have a C++ flavor, i e., they are shown by "//" to the end of the line. The Verilog language describes a digital system as a set of modules, but here we have only a single module called "simple".

2.1 A First Verilog Program

//By Dan Hyde; August 9, 1995
//A first digital model in Verilog
module simple;
// Simple Register Transfer Level (RTL) example to demo Verilog.
// The register A is incremented by one.  Then first four bits of B is
// set to "not" of the last four bits of A.  C is the "and" reduction
// of the last two bits of A.
//declare registers and flip-flops
reg [0:7] A, B;
reg       C;
// The two "initial"s and "always" will run concurrently
initial begin: stop_at
   // Will stop the execution after 20 simulation units.
   #20; $stop;    
end
// These statements done at simulation time 0 (since no #k)
initial begin: Init
    // Initialize the register A.  The other registers have values of "x"
    A = 0;   
  
    // Display a header
    $display("Time   A         B    C");  
            
    // Prints the values anytime a value of A, B or C changes
    $monitor("  %0d %b %b %b", $time, A, B, C);
end
//main_process will loop until simulation is over
always begin: main_process
    // #1 means do after one unit of simulation time
    #1 A = A + 1;
    #1 B[0:3] = ~A[4:7];  // ~ is bitwise "not" operator
    #1 C = &A[6:7];       // bitwise "and" reduction of last two bits
of A
    
end
endmodule

In module simple, we declared A and B as 8-bit registers and C a 1-bit register or flip-flop. Inside of the module, the one "always" and two "initial" constructs describe three threads of control, i. e., they run at the same time or concurrently. Within the initial construct, statements are executed sequentially much like in C or other traditional imperative programming languages. The always construct is the same as the initial construct except that it loops forever as long as the simulation runs.

The notation #1 means to execute the statement after delay of one unit of simulated time. Therefore, the thread of control caused by the first initial construct will delay for 20 time units before calling the system task $stop and stop the simulation.

The $display system task allows the designer to print a message much like printf does in the language C. Every time unit that one of the listed variables' value changes, the $monitor system task prints a message. The system function $time returns the current value of simulated time.

Below is the output of the VeriWell Simulator: (See Section 3 on how to use the VeriWell simulator.)

Time   A         B    C
  0 00000000 xxxxxxxx x
  1 00000001 xxxxxxxx x
  2 00000001 1110xxxx x
  3 00000001 1110xxxx 0
  4 00000010 1110xxxx 0
  5 00000010 1101xxxx 0
  7 00000011 1101xxxx 0
  8 00000011 1100xxxx 0
  9 00000011 1100xxxx 1
  10 00000100 1100xxxx 1
  11 00000100 1011xxxx 1
  12 00000100 1011xxxx 0
  13 00000101 1011xxxx 0
  14 00000101 1010xxxx 0
  16 00000110 1010xxxx 0
  17 00000110 1001xxxx 0
  19 00000111 1001xxxx 0
Stop at simulation time 20

You should carefully study the program and its output before going on. The structure of the program is typical of the Verilog programs you will write for this course, i. e., an initial construct to specify the length of the simulation, another initial construct to initialize registers and specify which registers to monitor and an always construct for the digital system you are modeling. Notice that all the statements in the second initial are done at time = 0, since there are no delay statements, i. e., #.

2.2 Lexical Conventions

The lexical conventions are close to the programming language C++. Comments are designated by // to the end of a line or by /* to */ across several lines. Keywords, e. g., module, are reserved and in all lower case letters. The language is case sensitive, meaning upper and lower case letters are different. Spaces are important in that they delimit tokens in the language.

Numbers are specified in the traditional form of a series of digits with or without a sign but also in the following form:

where contains decimal digits that specify the size of the constant in the number of bits. The is optional. The is the single character ' followed by one of the following characters b, d, o and h, which stand for binary, decimal, octal and hex, respectively. The part contains digits which are legal for the . Some examples:

  549 // decimal number
  'h 8FF // hex number
  'o765 // octal number
  4'b11 // 4-bit binary number 0011
  3'b10x // 3-bit binary number with least significant bit unknown
  5'd3 // 5-bit decimal number
  -4'b11 // 4-bit two's complement of 0011 or 1101

The part may not contain a sign. Any sign must go on the front.

A string is a sequence of characters enclosed in double quotes.

  "this is a string"

Operators are one, two or three characters and are used in expressions. See Section 2.5 for the operators.

An identifier is specified by a letter or underscore followed by zero or more letters, digits, dollar signs and underscores. Identifiers can be up to 1024 characters.

2.3 Program Structure

The Verilog language describes a digital system as a set of modules. Each of these modules has an interface to other modules to describe how they are interconnected. Usually we place one module per file but that is not a requirement. The modules may run concurrently, but usually we have one top level module which specifies a closed system containing both test data and hardware models. The top level module invokes instances of other modules.

Modules can represent bits of hardware ranging from simple gates to complete systems, e. g., a microprocessor. Modules can either be specified behaviorally or structurally (or a combination of the two). A behavioral specification defines the behavior of a digital system (module) using traditional programming language constructs, e. g., ifs, assignment statements. A structural specification expresses the behavior of a digital system (module) as a hierarchical interconnection of sub modules. At the bottom of the hierarchy the components must be primitives or specified behaviorally. Verilog primitives include gates, e. g., nand, as well as pass transistors (switches).

The structure of a module is the following:

  module  ();


endmodule

The is an identifier that uniquely names the module. The is a list of input, inout and output ports which are used to connect to other modules. The section specifies data objects as registers, memories and wires as wells as procedural constructs such as functions and tasks.

The may be initial constructs, always constructs, continuous assignments or instances of modules.

Here is a behavior specification of a module NAND. The output out is the not of the and of the inputs in1 and in2.

// Behavioral Model of a Nand gate
// By Dan Hyde, August 9, 1995
module NAND(in1, in2, out);
  input in1, in2;
  output out;
                 // continuous assign statement
  assign out = ~(in1 & in2);
endmodule

The ports in1, in2 and out are labels on wires. The continuous assignment assign continuously watches for changes to variables in its right hand side and whenever that happens the right hand side is re-evaluated and the result immediately propagated to the left hand side (out).

The continuous assignment statement is used to model combinational circuits where the outputs change when one wiggles the input.

Here is a structural specification of a module AND obtained by connecting the output of one NAND to both inputs of another one.

module AND(in1, in2, out);
// Structural model of AND gate from two NANDS
  input in1, in2;
  output out;
  wire w1;
                 // two instances of the module NAND
  NAND NAND1(in1, in2, w1);
  NAND NAND2(w1, w1, out);
endmodule

This module has two instances of the NAND module called NAND1 and NAND2 connected together by an internal wire w1.

The general form to invoke an instance of a module is :

();

where are values of parameters passed to the instance. An example parameter passed would be the delay for a gate.

The following module is a high level module which sets some test data and sets up the monitoring of variables.

module test_AND;
// High level module to test the two other modules
  reg a, b;
  wire out1, out2;
  initial begin  // Test data
     a = 0;  b = 0;
     #1 a = 1;  
     #1 b = 1;
     #1 a = 0;
  end
  initial begin // Set up monitoring
    $monitor("Time=%0d a=%b b=%b out1=%b out2=%b",
              $time, a, b, out1, out2);
  end
                // Instances of modules AND and NAND
  AND  gate1(a, b, out2);
  NAND gate2(a, b, out1);
endmodule

Notice that we need to hold the values a and b over time. Therefore, we had to use 1-bit registers. reg variables store the last value that was procedurally assigned to them (just like variables in traditional imperative programming languages). wires have no storage capacity. They can be continuously driven, e. g., with a continuous assign statement or by the output of a module, or if input wires are left unconnected, they get the special value of x for unknown.

Continuous assignments use the keyword assign whereas procedural assignments have the form = where the must be a register or memory. Procedural assignment may only appear in initial and always constructs.

The statements in the block of the first initial construct will be executed sequentially, some of which are delayed by #1, i. e., one unit of simulated time. The always construct behaves the same as the initialconstruct except that it loops forever (until the simulation stops). The initial and always constructs are used to model sequential logic (i. e., finite state automata).

Verilog makes an important distinction between procedural assignment and the continuous assignment assign . Procedural assignment changes the state of a register, i. e., sequential logic, whereas the continuous statement is used to model combinational logic. Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value. It is important to understand and remember the difference.

We place all three modules in a file and run the simulator to produce the following output.

Time=0 a=0 b=0 out1=1 out2=0
Time=1 a=1 b=0 out1=1 out2=0
Time=2 a=1 b=1 out1=0 out2=1
Time=3 a=0 b=1 out1=1 out2=0

Since the simulator ran out of events, I didn't need to explicit stop the simulation.

2.4 Data Types

2.4.1 Physical Data Types

Since the purpose of Verilog HDL is to model digital hardware, the primary data types are for modeling registers (reg) and wires (wire). The reg variables store the last value that was procedurally assigned to them whereas the wire variables represent physical connections between structural entities such as gates. A wire does not store a value. A wire variable is really only a label on a wire. (Note that the wire data type is only one of several net data types in Verilog HDL which include wired and (wand), wired or (wor) and tristate bus (tri). This handout is restricted to only the wire data type.)

The reg and wire data objects may have the following possible values:

  0 logical zero or false
1 logical one or true
x unknown logical value
z  high impedance of tristate gate

The reg variables are initialized to x at the start of the simulation. Any wire variable not connected to something has the x value.

You may specify the size of a register or wire in the declaration For example, the declarations

  reg [0:7] A, B;
  wire [0:3] Dataout;
  reg [7:0] C;

specify registers A and B to be 8-bit wide with the most significant bit the zeroth bit, whereas the most significant bit of register C is bit seven. The wire Dataout is 4 bits wide.

The bits in a register or wire can be referenced by the notation [:].

For example, in the second procedural assignment statement

  initial begin: int1
   A = 8'b01011010;
   B = {A[0:3] | A[4:7], 4'b0000};
  end

B is set to the first four bits of A bitwise or-ed with the last four bits of A and then concatenated with 0000. B now holds a value of 11110000. The {} brackets means the bits of the two or more arguments separated by commas are concatenated together.

The range referencing in an expression must have constant expression indices. However, a single bit may be referenced by a variable. For example:

  reg [0:7] A, B;
  B = 3;
  A[0: B] = 3'b111; // ILLEGAL - indices MUST be constant!!
  A[B] = 1'b1;      // A single bit reference is LEGAL

Why such a strict requirement of constant indices in register references? Since we are describing hardware, we want only expressions which are realizable.

Memories are specified as vectors of registers. For example, Mem is 1K words each 32-bits.

  reg [31:0] Mem [0:1023];

The notation Mem[0] references the zeroth word of memory. The array index for memory (register vector) may be a register. Notice that one can not reference at the bit-level of a memory in Verilog HDL. If you want a specific range of bits in a word of memory, you must first transfer the data in the word to a temporary register.

2.4.2 Abstract Data Types

In addition to modeling hardware, there are other uses for variables in a hardware model. For example, the designer might want to use an integer variable to count the number of times an event occurs. For the convenience of the designer, Verilog HDL has several data types which do not have a corresponding hardware realization. These data types include integer, real and time. The data types integer and real behave pretty much as in other languages, e. g., C. Be warned that a reg variable is unsigned and that an integer variable is a signed 32-bit integer. This has important consequences when you subtract.

time variables hold 64-bit quantities and are used in conjunction with the $time system function. Arrays of integer and time variables (but not reals) are allowed. Multiple dimensional arrays are not allowed in Verilog HDL. Some examples:

   integer Count;     // simple 32-bit integer
   integer K[1:64];   // an array of 64 integers
   time Start, Stop;  // Two 64-bit time variables

2.5 Operators

2.5.1 Binary Arithmetic Operators

Binary arithmetic operators operate on two operands. Register and net (wire) operands are treated as unsigned. However, real and integer operands may be signed. If any bit is unknown ('x') then result is unknown.

   Operator Name         Comments   + Addition
- Subtraction
* Multiplication
/ Division Divide by zero produces an x.
% Modulus

2.5.2 Unary Arithmetic Operators

  Operator Name         Comments   - Unary Minus Changes sign of its operand.

2.5.3 Relational Operators

Relational operators compare two operands and return a logical value, i. e., TRUE(1) or FALSE(0). If any bit is unknown, the relation is ambiguous and the result is unknown.

  Operator Name                Comments 
> Greater than
>= Greater than or equal
< equal  ="=">

2.5.4 Logical Operators

Logical operators operate on logical operands and return a logical value, i. e., TRUE(1) or FALSE(0). Used typically in if and while statements. Do not confuse logical operators with the bitwise Boolean operators. For example , ! is a logical NOT and ~ is a bitwise NOT. The first negates, e. g., !(5 == 6) is TRUE. The second complements the bits, e. g., ~{1,0,1,1} is 0100.

 Operator Name Comments   ! Logical negation
&& Logical AND
|| Logical OR

2.5.5 Bitwise Operators

Bitwise operators operate on the bits of the operand or operands. For example, the result of A & B is the AND of each corresponding bit of A with B. Operating on an unknown (x) bit results in the expected value. For example, the AND of an x with a FALSE is an x. The OR of an x with a TRUE is a TRUE.

 Operator Name Comments   ~  Bitwise negation
&  Bitwise AND
|  Bitwise OR
^  Bitwise XOR
~&  Bitwise NAND
~|  Bitwise NOR
~^ or ^~ Equivalence Bitwise NOT XOR

2.5.6 Unary Reduction Operators

Unary reduction operators produce a single bit result from applying the operator to all of the bits of the operand. For example, &A will AND all the bits of A.

 Operator Name Comments   & AND reduction
| OR reduction
^ XOR reduction
~& NAND reduction
~| NOR reduction
~^ XNOR reduction

2.5.7 Other Operators

The conditional operator operates much like in the language C.

Operator Name Comments 
=== Case equality The bitwise comparison includes comparison of x and z
                  values.  All bits must match for equality.  Returns TRUE
                  or FALSE.
!== Case inequality The bitwise comparison includes comparison of x and z
                  values.  Any bit difference produces inequality.  Returns
                  TRUE or FALSE.
{ , } Concatenation Joins bits together with 2 or more comma-separated expressions,
                  e, g. {A[0], B[1:7]} concatenates the zeroth bit of A to
                  bits 1 to 7 of B.
<<>A = A <<> shifts A two bits to left with zero fill.
>> Shift right Vacated bit positions are filled with zeros.
?: Conditional Assigns one of two values depending on the conditional
                  expression.  E. g., A = C>D ? B+3 : B-2  means
                  if C greater than D, the value of A is B+3 otherwise B-2.

2.5.8 Operator Precedence

The precedence of operators is shown below. The top of the table is the highest precedence and the bottom is the lowest. Operators on the same line have the same precedence and associate left to right in an expression. Parentheses can be used to change the precedence or clarify the situation. We strongly urge you to use parentheses to improve readability.

unary operators: !  &  ~&  |  ~|  ^  ~^  +  -   (highest precedence)
*  /  %
+  -
<<  >>
<  <=  >  >+
==  !=  ===  ~==
&  ~&amp;amp;amp;amp;amp;  ^  ~^
|  ~|
&&
||
?:

2.6 Control Constructs

Verilog HDL has a rich collection of control statements which can used in the procedural sections of code, i. e., within an initial or always block. Most of them will be familiar to the programmer of traditional programming languages like C. The main difference is instead of C's { } brackets, Verilog HDL uses begin and end. In Verilog, the { } brackets are used for concatenation of bit strings. Since most users are familiar with C, the following subsections typically show only an example of each construct.

2.6.1 Selection - if and case Statements

The if statement is easy to use.

    if (A == 4)
       begin
         B = 2;
       end
    else
       begin
         B = 4;
       end

Unlike the case statement in C, the first that matches the value of the is selected and the associated statement is executed then control is transferred to after the endcase, i. e., no break statements are needed as in C.

    case ()
      : 
      : 
      default: 
    endcase

The following example checks a 1-bit signal for its value.

    case (sig)
      1'bz: $display("Signal is floating");
      1'bx: $display("Signal is unknown");
      default: $display("Signal is %b", sig);
    endcase

2.6.2 Repetition - for, while and repeat Statements

The for statement is very close to C's for statement except that the ++ and -- operators do not exist in Verilog. Therefore, we need to use i = i + 1.

    for(i = 0; i < i =" i">
      begin
        $display("i= %0d", i);
      end

The while statement acts in the normal fashion.

    i = 0;
    while(i <>
       begin
         $display("i= %0d", i);
         i = i + 1;
       end

The repeat statement repeats the following block a fixed number of times, in this example, five times.

    repeat (5)
       begin
         $display("i= %0d", i);
         i = i + 1;
       end

2.7 Other Statements

2.7.1 parameter Statement

The parameter statement allows the designer to give a constant a name. Typical uses are to specify width of registers and delays. For example, the following allows the designer to parameterized the declarations of a model.

  parameter byte_size = 8;
  reg [byte_size - 1:0] A, B;

2.7.2 Continuous Assignment

Continuous assignments drive wire variables and are evaluated and updated whenever an input operand changes value. The following ands the values on the wires in1 and in2 and drives the wire out. The keyword assign is used to distinguish the continuous assignment from the procedural assignment. See Section 2.3 for more discussion on continuous assignment.

  assign out = ~(in1 & in2);

2.7.3 Blocking and Non-blocking Procedural Assignments

The Verilog language has two forms of the procedural assignment statement: blocking and non-blocking. The two are distinguished by the = and <= assignment operators. The blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement. The non-blocking (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit. For example, the following Verilog program

// testing blocking and non-blocking assignment
module blocking;
reg [0:7] A, B;
initial begin: init1
        A = 3;
        #1 A = A + 1;   // blocking procedural assignment
           B = A + 1;
           $display("Blocking:     A= %b B= %b", A, B );
        A = 3;
        #1 A <= A + 1;  // non-blocking procedural assignment
           B <= A + 1;
          
        #1 $display("Non-blocking: A= %b B= %b", A, B ); 
end
endmodule

produces the following output:

Blocking:     A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100

The effect is for all the non-blocking assignments to use the old values of the variables at the beginning of the current time unit and to assign the registers new values at the end of the current time unit. This reflects how register transfers occur in some hardware systems.

2.8 Tasks and Functions

Tasks are like procedures in other programming languages, e. g., tasks may have zero or more arguments and do not return a value. Functions act like function subprograms in other languages. Except:

1. A Verilog function must execute during one simulation time unit. That is, no time controlling statements, i. e., no delay control (#), no event control (@) or wait statements, allowed. A task can contain time controlled statements.

2. A Verilog function can not invoke (call, enable) a task; whereas a task may call other tasks and functions.

The definition of a task is the following:

  task ;   // Notice: no list inside ()s    
 
 
endtask

An invocation of a task is of the following form:

();

where is a list of expressions which correspond to the of the definition. Port arguments in the definition may be input, inout or output. Since the in the task definition look like declarations, the programmer must be careful in adding declares at the beginning of a task.

// Testing tasks and functions
// Dan Hyde, Aug 28, 1995
module tasks;
task add;      // task definition
 input a, b;   // two input argument ports
 output c;     // one output argument port
 reg R;        // register declaration
 begin
   R = 1;
   if (a == b)
     c = 1 & R;
   else
     c = 0;
 end
endtask
initial begin: init1
   reg p;
   add(1, 0, p);  // invocation of task with 3 arguments
   $display("p= %b", p);    
end
endmodule

input and inout parameters are passed by value to the task and output and inout parameters are passed back to invocation by value on return. Call by reference is not available.

Allocation of all variables is static. Therefore, a task may call itself but each invocation of the task uses the same storage, i. e., the local variables are not pushed on a stack. Since concurrent threads may invoke the same task, the programmer must be aware of the static nature of storage and avoid unwanted overwriting of shared storage space.

The purpose of a function is to return a value that is to be used in an expression. A function definition must contain at least one input argument. The passing of arguments in functions is the same as with tasks (see above). The definition of a function is the following:

 function  ; // Notice: no list inside ()s   


endfunction

where is the type of the results passed back to the expression where the function was called. Inside the function, one must assign the function name a value. Below is a function which is similar to the task above.

// Testing functions
// Dan Hyde, Aug 28, 1995
module functions;
function [1:1] add2; // function definition
 input a, b;         // two input argument ports
 reg R;              // register declaration
 begin
   R = 1;
   if (a == b)
     add2 = 1 & R;
   else
     add2 = 0;
 end
endfunction
initial begin: init1
   reg p;
   p = add2(1, 0);  // invocation of function with 2 arguments
   $display("p= %b", p);    
end
endmodule

2.9 Timing Control

The Verilog language provides two types of explicit timing control over when simulation time procedural statements are to occur. The first type is a delay control in which an expression specifies the time duration between initially encountering the statement and when the statement actually executes. The second type of timing control is the event expression, which allows statement execution. The third subsection describes the wait statement which waits for a specific variable to change.

Verilog is a discrete event time simulator, i. e., events are scheduled for discrete times and placed on an ordered-by-time wait queue. The earliest events are at the front of the wait queue and the later events are behind them. The simulator removes all the events for the current simulation time and processes them. During the processing, more events may be created and placed in the proper place in the queue for later processing. When all the events of the current time have been processed, the simulator advances time and processes the next events at the front of the queue.

If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following:

1. gate or wire delay, if specified.

2. a delay control, introduced by the # symbol.

3. an event control, introduced by the @ symbol.

4. the wait statement.

The order of execution of events in the same clock time may not be predictable.

2.9.1 Delay Control ( #)

A delay control expression specifies the time duration between initially encountering the statement and when the statement actually executes. For example:

  #10 A = A + 1;

specifies to delay 10 time units before executing the procedural assignment statement. The # may be followed by an expression with variables.

2.9.2 Events

The execution of a procedural statement can be triggered with a value change on a wire or register, or the occurrence of a named event. Some examples:

 @r begin                  // controlled by any value change in 
  A = B&C;                 // the register r
 end
 @(posedge clock2) A = B&C;   // controlled by positive edge of clock2
 @(negedge clock3) A = B&C;   // controlled by negative edge of clock3
 forever @(negedge clock)     // controlled by negative edge
  begin
  A = B&C;
 end

In the forms using posedge and negedge, they must be followed by a 1-bit expression, typically a clock. A negedge is detected on the transition from 1 to 0 (or unknown). A posedge is detected on the transition from 0 to 1 (or unknown).

Verilog also provides features to name an event and then to trigger the occurrence of that event. We must first declare the event:

  event event6;

To trigger the event, we use the -> symbol :

  -> event6;

To control a block of code, we use the @ symbol as shown:

  @(event6)  begin
   
  end

We assume that the event occurs in one thread of control, i. e., concurrently, and the controlled code is in another thread. Several events may to or-ed inside the parentheses.

2.9.3 Wait Statement

The wait statement allows a procedural statement or a block to be delayed until a condition becomes true.

  wait (A == 3)
  begin
      A = B&C;
  end

The difference between the behavior of a wait statement and an event is that the wait statement is level sensitive whereas @(posedge clock); is triggered by a signal transition or is edge sensitive.

2.10 Traffic Light Example

To demonstrate tasks as well as events, we will show a hardware model of a traffic light.

// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35, 
          amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
   #1000; $stop;    
end
// initialize the lights and set up monitoring of registers
initial begin: Init
    red = off; amber = off; green = off;
    $display("                 Time green amber red");  
    $monitor("%3d    %b     %b    %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
   output color;
   input [31:0] tics;
   begin
      repeat(tics)  // wait to detect tics positive edges on clock
         @(posedge clock);
      color = off;
   end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
  #1 clock = 0;
  #1 clock = 1;
end
always begin: main_process
   red = on;
   light(red, red_tics);  // call task to wait 
   green = on;
   light(green, green_tics);
   amber = on;
   light(amber, amber_tics);
end
endmodule

The output of the traffic light simulator is the following:

                 Time green amber red
                   0    0     0    1
                  70    1     0    0
                 110    0     1    0
                 116    0     0    1
                 186    1     0    0
                 226    0     1    0
                 232    0     0    1
                 302    1     0    0
                 342    0     1    0
                 348    0     0    1
                 418    1     0    0
                 458    0     1    0
                 464    0     0    1
                 534    1     0    0
                 574    0     1    0
                 580    0     0    1
                 650    1     0    0
                 690    0     1    0
                 696    0     0    1
                 766    1     0    0
                 806    0     1    0
                 812    0     0    1
                 882    1     0    0
                 922    0     1    0
                 928    0     0    1
                 998    1     0    0
Stop at simulation time 1000

3. Using the VeriWell Simulator

3.1 Creating the Model File

Enter the Verilog code using your favorite editor. We recommend that you use ".v" as the extension on the source file.

3.2 Starting the Simulator

VeriWell is run from the UNIX shell window. Type "veriwell" followed by the names of the files containing the models and the options. The options can appear in any order and anywhere on the command line. For example:

  host-name% veriwell cpu.v bus.v top.v -s

This will load each of the files into memory, compile them, and enter interactive mode. Removing the "-s" option would cause the simulation to begin immediately. Options are processed in the order that they appear on the command line. Files are processed in the order that they appear after the options are processed.

3.3 How to Exit the Simulator?

To exit the simulator, you can type $finish; or press Control-d.

To stop the simulation, you press Control-c. Executing a $stop system task in the code will also stop the simulation.

3.4 Simulator Options

Commonly used options typed on the command line are shown below. One should consult the VeriWell User's Guide for the others.

-i

Specifies a file that contains interactive commands to be executed as soon as interactive command mode is entered. This option should be used with the "-s" option. This can be used to initialize variables and set time limits on the simulation.

-s

Causes interactive mode to be entered before the simulation begins.

-t

Causes all statements to be traced. Trace mode may be disabled with the $cleartrace system task.

3.5 Debugging Using VeriWell's Interactive Mode

VeriWell is interactive. Once invoked, the simulation can be controlled with simple commands. Also, VeriWell accepts any Verilog statement (but new modules or declarations cannot be added).

Interactive mode is entered in one of three ways:

1). When the "-s" option is used on the command line (or in a command file), interactive mode is entered before the simulation begins,

2). When the simulation encounters the $stop system task, or,

3). When the user types Control-c during simulation (but not during compilation).

Interactive Commands

 Continue ('.') [period]
Resume execution from the current location.

Single-step with trace (',') [comma]
Execute a single statement and display the trace for that statement.

Single-step without trace (';') [semicolon]
Execute a single statement without trace.

Current location (':') [colon]
Display the current location.

Control-d or $finish;
Exit VeriWell simulator.

Typically, the kinds of Verilog statements executed interactively are used for debugging and information-gathering. $display and $showvars can be typed at the interactive prompt to show the values of variables. Notice the complete system task statement must be typed including parameters and semicolon. $scope(); and $showscopes; can be typed to traverse the model hierarchy. $settrace; and $cleartrace; will enter and exit trace mode. Typing "#100; $stop;" will stop the execution after 100 simulation units.

4. System Tasks and Functions

System tasks are not part of the Verilog language but are build-in tasks contained in a library. A few of the more commonly used one are described below. The Verilog Language Reference Manual has many more.

4.1 $cleartrace

The $cleartrace system task turns off the trace. See $settrace system task to set the trace.

  $cleartrace;

4.2 $display

Displays text to the screen much like the printf statement from the language C. The general form is

  $display(, , ... );

where may be a quoted string, an expression that returns a value or a null parameter. For example, the following displays a header.

  $display("Registers:   A   B   C");

The special character % indicates that the next character is a format specification. For each % character that appears in the string, a corresponding expression must be supplied after the string. For example, the following prints the value of A in binary, octal, decimal and hex.

  $display("A=%b binary %o octal %d decimal %h hex",A,A,A,A);

produces the following output

A=00001111 binary 017 octal  15 decimal 0f hex

The commonly used format specifiers are

  %b  display in binary format
%c display in ASCII character format
%d display in decimal format
%h display in hex format
%o display in octal format
%s display in string format

A 0 between the % and format specifier allocates the exact number of characters required to display the expression result, instead of the expression's largest possible value (the default). For example, this is useful for displaying the time as shown by the difference between the following two $display statements.

  $display("Time = %d", $time);
  $display("Time = %0d", $time);

produces the following output

Time =                    1
Time = 1

Escape sequences may be included in a string. The commonly used escape sequences are the following:

  \n the newline character
\t the tab character
\\ the \ character
\" the " character
%% the percent sign

A null parameter produces a single space character in the display. A null parameter is characterized by two adjacent commas in the parameter list.

Note that $display automatically adds a newline character to the end of its output. See $write in Verilog Language Reference Manual if you don't want a newline.

4.3 $finish

The $finish system task exits the simulator to the host operating system. Don't forget to type the semicolon while in interactive mode.

   $finish;

4.4 $monitor

The $monitor system task provides the ability to monitor and display the values of any variable or expression specified as parameters to the task. The parameters are specified in exactly the same manner as the $display system task. When you invoke the $monitor task, the simulator sets up a mechanism whereby each time a variable or an expression in the parameter list changes value, with the exception of $time, the entire parameter list is displayed at the end of the time step as if reported by the $display task. If two or more parameters change values at the same time, however, only one display is produced. For example, the following will display a line anytime one of the registers A, B or C changes.

   $monitor("  %0d %b %b "%b, $time, A, B, C);

Only one $monitor statement may be active at any one time. The monitoring may be turned off and on by the following:

  $monitoroff;
    
  $monitoron;

4.5 $scope

The $scope system task lets the user assign a particular level of hierarchy as the interactive scope for identifying objects. $scope is useful during debugging as the user may change the scope to inspect the values of variables in different modules, tasks and functions.

  $scope();

The parameter must be the complete hierarchical name of a module, task, function or named block. See $showscopes system task to display the names.

4.6 $settrace

The $settrace system task enables tracing of simulation activity. The trace consists of various information, including the current simulation time, the line number, the file name, module and any results from executing the statement.

  $settrace;

You can turn off the trace using the $cleartrace system task.

4.7 $showscopes

The $showscopes system task displays a complete lists of all the modules, tasks, functions and named blocks that are defined at the current scope level.

  $showscopes;  
4.8
$showvars
 
The $showvars system task produces status information for
register and net (wires) variables, both scalar and vector.  When invoked
without parameters, $showvars displays the status of all
variables in the current scope.  When invoked with a list of variables, it
shows only the status of the specified variables.

  $showvars;
$showvars(); 


4.9
$stop



The $stop system task puts the simulator into
a halt mode, issues an interactive command prompt  and passes control to the
user.  See Section 3.5 on using VeriWell's interactive mode.

  $stop; 


4.10
$time
 
The $time system function returns the current simulation time
as a 64-bit integer.  $time must be used in an expression.



References

1. Cadence Design Systems, Inc., Verilog-XL Reference Manual.


2. Open Verilog International (OVI), Verilog HDL Language Reference Manual
(LRM), 15466 Los Gatos Boulevard, Suite 109-071, Los Gatos, CA 95032; Tel:
(408)353-8899, Fax: (408) 353-8869, Email: OVI@netcom.com, $100.


3. Sternheim, E. , R. Singh, Y. Trivedi, R. Madhaven and W. Stapleton,
Digital Design and Synthesis with Verilog HDL, published by Automata
Publishing Co., Cupertino, CA, 1993, ISBN 0-9627488-2-X, $65.


4. Thomas, Donald E., and Philip R. Moorby, The Verilog Hardware Description
Language, second edition, published by Kluwer Academic Publishers, Norwell
MA, 1994, ISBN 0-7923-9523-9, $98, includes DOS version of VeriWell simulator
and programs on diskette.


5. Wellspring Solutions, Inc., VeriWell User's Guide 1.2, August,
1994, part of free distribution of VeriWell, available online.


6. World Wide Web Pages:

FAQ for comp.lang.verilog - http://www.cray.com/verilog/verilog-faq.html

comp.lang.verilog archives - http://www.cray.com/verilog/archive.html

Cadence Design Systems, Inc. - http://www.cadence.com/

Wellspring Solutions, Inc. - ftp://iii.net/pub/pub-site/wellspring

Verilog research at Cambridge, England -
http://www.cl.cam.uk/users/mjcg/Verilog/

Core 2 Duo Vs. Core Duo

2007-01-09T20:55:00.000-08:00

Core 2 Duo Vs Core Duo

BFM - Bus functional Model

2007-01-09T04:06:00.000-08:00

Bus functional models are simplified simulation models that accurately reflect the I/O level behavior of a device without modeling its internal computational abilities. For example, a bus functional model of a microprocessor would be able to generate PCI read and write transactions to a PCI device model to initialize and test the PCI device's functionality, but the microprocessor BFM would not be capable of reading CPU instructions from a memory and properly executing the instructions (this would require a complete behavioral level model of the processor). Bus functional models are commonly used in test benches to stimulate design models and verify their functionality

GAIM: Connect and Use Google's Gtalk Servers

2007-01-02T04:01:00.000-08:00

Since gtalk is based on jabber, however, you can use it with any jabber compatable client. Here is how to use the wonderful freeware program GAIM to connect to the gtalk/google servers.

GAIM

Tools

Accounts

Add

Jabber

screen name

gmail.com

Gaim

password

alias

Show More Options

Use TLS if available

talk.google.com

Save

Ref: http://www.tech-recipes.com/instant_messaging_tips1180.html

Keywords: gtalk, gaim, google talk

LFSR - Linear Feedback Shift Registers

2006-12-21T22:44:00.000-08:00

Linear Feedback Shift Register (LFSR), in which the output from a standard shift register is cunningly manipulated and fed back into its input in such a way as to cause the function to endlessly cycle through a sequence of patterns.

Many-to-one implementations
LFSRs are simple to construct and are useful for a wide variety of applications, but are often sadly neglected by designers. One of the more common forms of LFSR is formed from a simple shift register with feedback from two or more points, or taps, in the register chain (Fig 1).

1. LFSR with XOR feedback path.

The taps in this example are at bit 0 and bit 2, and can be referenced as [0,2]. All of the register elements share a common clock input, which is omitted from the symbol for reasons of clarity. The data input to the LFSR is generated by XOR-ing or XNOR-ing the tap bits; the remaining bits function as a standard shift register. The sequence of values generated by an LFSR is determined by its feedback function (XOR versus XNOR) and tap selection. For example, consider two 3-bit XOR based LFSRs with different tap selections (Fig 2).

2. Comparison of alternative tap selections.

Both LFSRs start with the same initial value but, due to the different taps, their sequences rapidly diverge as clock pulses are applied. In some cases an LFSR will end up cycling round a loop comprising a limited number of values. However, both of the LFSRs shown in Fig 2 are said to be of maximal length because they sequence through every possible value (excluding all of the bits being 0) before returning to their initial values.

A binary field with 'n' bits can assume 2^n unique values, but a maximal-length LFSR with 'n' register bits will only sequence through (2^n – 1) values. This is because LFSRs with XOR feedback paths will not sequence through the value where all the bits are 0, while their XNOR equivalents will not sequence through the value where all the bits are 1 (Fig 3).

3. Comparison of XOR versus XNOR feedback paths.

Verilog Free Simulator and Viewer

2006-12-18T07:09:00.000-08:00

Icarus Verilog : This is best Free Verilog simulator out there, it is simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. Icarus continues to get better and better. Icarus is being used for real design work by companies now as a simulator, and is starting to be useful as a synthesizer for a Xilinx FPGA flow as well.
Dinotrace : Freeware VCD viewer from veritools

I have tested above combination on linux. Both works fine...and is good to start with.

Sample Design:
^^^^^^^^^^^^
//-----------------------------------------------------
module encoder_using_if(
binary_out , // 4 bit binary output
encoder_in , // 16-bit input
enable // Enable for the encoder
);
//-----------Output Ports---------------
output [3:0] binary_out ;
//-----------Input Ports---------------
input enable ;
input [15:0] encoder_in ;
//------------Internal Variables--------
reg [3:0] binary_out ;
//-------------Code Start-----------------
always @ (enable or encoder_in)
begin
binary_out = 0;
if (enable) begin
if (encoder_in == 16'h0002) begin
binary_out = 1;
end if (encoder_in == 16'h0004) begin
binary_out = 2;
end if (encoder_in == 16'h0008) begin
binary_out = 3;
end if (encoder_in == 16'h0010) begin
binary_out = 4;
end if (encoder_in == 16'h0020) begin
binary_out = 5;
end if (encoder_in == 16'h0040) begin
binary_out = 6;
end if (encoder_in == 16'h0080) begin
binary_out = 7;
end if (encoder_in == 16'h0100) begin
binary_out = 8;
end if (encoder_in == 16'h0200) begin
binary_out = 9;
end if (encoder_in == 16'h0400) begin
binary_out = 10;
end if (encoder_in == 16'h0800) begin
binary_out = 11;
end if (encoder_in == 16'h1000) begin
binary_out = 12;
end if (encoder_in == 16'h2000) begin
binary_out = 13;
end if (encoder_in == 16'h4000) begin
binary_out = 14;
end if (encoder_in == 16'h8000) begin
binary_out = 15;
end
end
end
endmodule

TestBench:
`timescale 1ns/1ps
`include "encoder_using_if.v"
module encoder_test;
wire [3:0] binary_out;
reg enable;
reg [15:0] encoder_in;

encoder_using_if encode(.binary_out (binary_out), .encoder_in (encoder_in) , .enable (enable));

initial begin
#1 enable = 0;
encoder_in = 16'h0;

#2 enable = 1;
encoder_in = 16'h0001;

#3
encoder_in = 16'h0010;
#1 $finish;
end
initial begin
$monitor("Encoder out = %h \n",binary_out);
end
//always @ (enable or encoder_in)
initial
begin
$dumpfile( "foo.vcd" );
$dumpvars( 0, encoder_test );
end
endmodule

Command Used:
^^^^^^^^^^^^^

iverilog testbench.v
./a.out
./dinotrace foo.vcd

Keywords: Verilog, free simulator, waveform viewer, Icarus Verilog, Dinotrace

Latex

2006-12-18T02:59:00.000-08:00

What is TeX

TeX (pronounced "Tech") is mainly a low level programming language aimed to typesetting documents. It is very powerful but, since you have to take care of everything, it is difficult and time-consuming to use it for long documents.

What is LaTeX

LaTeX (pronounced either "Lah-tech" or "Lay-tech") is a macro package created by Leslie Lamport based on the TeX typesetting language of Donald Knuth. Its purpose is to produce professional looking and correctly typeset documents, in particular those with mathematical formulae. It is currently maintained by the LaTeX3 project. Numerous authors have contributed extensions, called packages or styles, to LaTeX. A number of these is usually bundled with a TeX/LaTeX software distribution or can be found in the Comprehensive TeX Archive Network (CTAN).

Since LaTeX comprises a group of TeX commands, LaTeX document processing follows a programming perspective. One creates a text file in LaTeX markup, which is then to be read by the LaTeX macro, which produces the final document.

Obviously, this has its disadvantages, compared with a WYSIWYG (What You See Is What You Get) program such as Openoffice.org Writer or Microsoft Word.

One can't see the final result straight away.
One needs to know the necessary commands for LaTeX markup.
It can sometimes be difficult to obtain a certain 'look'.

On the other hand, there are certain advantages to the markup language approach:

The layout, fonts, tables, etc. is consistent throughout.
Mathematical formulae can be easily typeset.
Indexes, footnotes, references, etc., are generated easily.
It encourages correctly structured documents.

The LaTeX-like approach can be called WYSIWYM, i.e. What You See Is What You Mean: you can't see how the final version will look like while typing, but you can see only the logical structure of the document, LaTeX will take care of the formatting for you.

The LaTeX document is a plain text file containing the content of the document, with additional markup. When the source file is processed by the macro package, it can produce documents in several formats such as DVI, PDF or PostScript.

Prerequisites

At a minimum, you'll need the following programs to edit LaTeX:

An editor (You can use a basic text editor like notepad, but a dedicated LaTeX editor will be more useful).
- On Windows, TeXnicCenter([1]) is a popular free and open source LaTeX editor.
- On *nix (including Mac OS X) systems, Emacsen and gvim provide powerful TeX enviroments for the tech-savvy, while Texmaker and Kile [2] provide more user-friendly development environments.
The LaTeX binaries and style sheets - e.g. MiKTeX [3] for Windows, teTeX [4] for Linux and teTeX for Mac OS X [5].
A DVI viewer to view and print the final result. Usually, a DVI viewer is included in the editor or is available with the binary distribution.

A distribution of LaTeX, with many packages, add-ins, editors and viewers for Unix, Linux, Mac and Windows can be obtained from the TeX users group at http://www.tug.org/texlive/.

Applications within a distribution

Here are the main programs you expect to find in any (La)TeX distribution:

tex: the simplest compiler, it gets a TeX file and creates DVI
pdftex: it gets a TeX file, but creates a PDF file
latex: the most used one: it gets a LaTeX file and creates a DVI
pdflatex: from a LaTeX creates a PDF
dvi2ps: converts the DVI file to PostScript
dvipdfm: converts the DVI file to PDF

When LaTeX was created, the only format it could create was DVI; then the PDF support was added by pdflatex, even if several people still don't use it. As it is clear from this short list, PDF files can be created with both pdflatex and dvipdfm; anyway, the output of pdflatex is much better than the other. DVI is an old format, and it does not support hyperlinks for example, while PDF does, so passing through DVI you will bring all the bad points of that format to PDF. Moreover the general output will be better using only pdflatex.

Strictly speaking, the document you are writing should be sightly different according to the compiler you are using (latex or pdflatex), but as we will see later, it is possible to add a sort of abstraction layer so to ignore what you are using, the applications will do everything by themselves.

Note that, since LaTeX is just a collection of macros for TeX, if you compile a plain TeX document with a LaTeX compiler (such as pdflatex) it will work, while the opposite is not true: if you try to compile a LaTeX source with a TeX compiler you will get only a lot of errors.

The following diagram shows the relationships between the (La)TeX source code and all the formats you can create from it:

The boxed red text represents the file formats, the blue text on the arrows represents the commands you have to use, the small dark green text under the boxes represents the image formats that are supported. Anytime you pass through an arrow you lose some information, that might decrease the quality of your document. Therefore, in order to achieve the highest quality in your output file, you should choose the shortest route to reach your target format. This is probably the most convenient way to obtain an output in your desired format anyway. Starting from a LaTeX source, the best way is to use only latex for a DVI output or pdflatex for a PDF output, converting to PostScript only when it is necessary to do it to print the document.

Most of the programs should be already within your LaTeX distribution, the others come with Ghostscript, that is a free and multi-platform software as well.

Reference: http://en.wikibooks.org/wiki/LaTeX/Introduction

Script use for compilation, and dvi to PDF file conversion

run.pl:

#!/usr/bin/perl
my $text1 = shift @ARGV or die print "No tex file is given as input\n";
#print "Inputed argument is $text1\n";
chop;
my @fname = split(/\./,$text1);
#print "Input array is @fname \n";
#print "Input text is $fname[0] . $fname[1] \n";

system("latex $text1");
system("dvips -Ppdf $fname[0].dvi");
system("ps2pdf $fname[0].ps $fname[0].pdf");
system("xpdf $fname[0].pdf");

Usage: ./run.pl filename.tex - Gives you PDF file as output directly

Keywords: Latex, Tex, PDF writer, dvi to pdf conversion

RISC Vs CISC

2006-12-14T21:06:00.000-08:00

RISC

The concept was developed by John Cocke of IBM Research during 1974. His argument was based upon the notion that a computer uses only 20% of the instructions, making the other 80% superfluous to requirement. A processor based upon this concept would use few instructions, which would require fewer transistors, and make them cheaper to manufacture. By reducing the number of transistors and instructions to only those most frequently used, the computer would get more done in a shorter amount of time. The term 'RISC' (short for Reduced Instruction Set Computer) was later coined by David Patterson, a teacher at the University of California in Berkeley.

The RISC concept was used to simplify the design of the IBM PC/XT, and was later used in the IBM RISC System/6000 and Sun Microsystems' SPARC microprocessors. The latter CPU led to the founding of MIPS Technologies, who developed the M.I.P.S. RISC microprocessor (Microprocessor without Interlocked Pipe Stages). Many of the MIPS architects also played an instrumental role in the creation of the Motorola 68000, as used in the first Amigas (MIPS Technologies were later bought by Silicon Graphics).. The MIPS processor has continued development, remaining a popular choice in embedded and low-end market. At one time, it was suspected the Amiga MCC would use this CPU to reduce the cost of manufacture. However, the consumer desktop market is limited, only the PowerPC processor remains popular in the choice of RISC alternatives. This is mainly due to Apple's continuous use of the series for its PowerMac range.

CISC

CISC (Complex Instruction Set Computer) is a retroactive definition that was introduced to distinguish the design from RISC microprocessors. In contrast to RISC, CISC chips have a large amount of different and complex instruction. The argument for its continued use indicates that the chip designers should make life easier for the programmer by reducing the amount of instructions required to program the CPU. Due to the high cost of memory and storage CISC microprocessors were considered superior due to the requirements for small, fast code. In an age of dwindling memory hard disk prices, code size has become a non-issue (MS Windows, hello?). However, CISC-based systems still cover the vast majority of the consumer desktop market. The majority of these systems are based upon the x86 architecture or a variant. The Amiga, Atari, and pre-1994 Macintosh systems also use a CISC microprocessor.

RISC Vs. CISC

The argument over which concept is better has been repeated over the past few years. Macintosh owners have elevated the argument to a pseudo religious level in support of their RISC-based God (the PowerPC sits next to the Steve Jobs statue on every Mac altar). Both positions have been blurred by the argument that we have entered a Post-RISC stage.

RISC: For and Against
RISC supporters argue that it the way of the future, producing faster and cheaper processors - an Apple Mac G3 offers a significant performance advantage over its Intel equivalent. Instructions are executed over 4x faster providing a significant performance boost! However, RISC chips require more lines of code to produce the same results and are increasingly complex. This will increase the size of the application and the amount of overhead required. RISC developers have also failed to remain in competition with CISC alternatives. The Macintosh market has been damaged by several problems that have affected the availability of 500MHz+ PowerPC chips. In contrast, the PC compatible market has stormed ahead and has broken the 1GHz barrier. Despite the speed advantages of the RISC processor, it cannot compete with a CISC CPU that boasts twice the number of clock cycles.
CISC: For and Against
As discussed above, CISC microprocessors are more expensive to make than their RISC cousins. However, the average Macintosh is more expensive than the WIntel PC. This is caused by one factor that the RISC manufacturers have no influence over - market factors. In particular, the WIntel market has become the definition of personal computing, creating a demand from people who have not used a computer previous. The x86 market has been opened by the development of several competing processors, from the likes of AMD, Cyrix, and Intel. This has continually reduced the price of a CPU of many months. In contrast, the PowerPC Macintosh market is dictated by Apple. This reduces the cost of x86 - based microprocessors, while the PowerPC market remains stagnant.

Post-RISC

As the world enters the 21st century the CISC Vs. RISC arguments have been swept aside by the recognition that neither terms are accurate in their description. The definition of 'Reduced' and 'Complex' instructions has begun to blur, RISC chips have increased in their complexity (compare the PPC 601 to the G4 as an example) and CISC chips have become more efficient. The result are processors that are defined as RISC or CISC only by their ancestry. The PowerPC 601, for example, supports more instructions than the Pentium. Yet the Pentium is a CISC chip, while the 601 is considered to be RISC. CISC chips have also gained techniques associated with RISC processors. Intel describe the Pentium II as a CRISC processor, while AMD use a RISC architecture but remain compatible with the dominant x86 CISC processors. Thus it is no longer important which camp the processor comes from, the emphasis has once-again been placed upon the operating system and the speed that it can execute instructions.

EPIC

In the aftermath of the CISC-RISC conflict, a new enemy has appeared to threaten the peace. EPIC (Explicitly Parallel Instruction Computing) was developed by Intel for the server market, thought it will undoubtedly appear in desktops over the next few years. The first EPIC processor will be the 64-bit Merced, due for release sometime during 2001 (or 2002, 2003, etc.). The market may be divided between combined CISC-RISC systems in the low-end and EPIC in the high-end.

Famous RISC microprocessors

ARM

One of the most well known RISC developers is Cambridge based Advanced Research Machines (originally Acorn Research Machines). Their ARM and StrongARM chips power the old Acorn Archimedes and the Apple Newton handwriting recognition systems. Since the unbundling of ARM from Acorn, Intel have invested a considerable amount of money in the company and have utilized the technology in their processor design.

Keywords: RISC, CISC, RISC Vs CISC, ARM, DSP Processor

IEEE 754 - Floating Point number representation at a Glance

2006-12-13T20:59:00.000-08:00

IEEE 754 at a Glance
A floating-point number representation on a computer uses something similar to a scientific notation with a base and an exponent. A scientific representation of 30,064,771 is 3.0064771 x 10⁷, whereas 1.001 can be written as 1.001 x 10⁰.

In the first example, 3.0064771 is called the mantissa, 10 the exponent base, and 7 the exponent.

IEEE standard 754 specifies a common format for representing floating-point numbers in a computer. Two grades of precision are defined: single precision and double precision. The representations use 32 and 64 bits, respectively. This is shown in Figure 2.

(Click to enlarge)
Figure 2: IEEE floating-point formats

In IEEE 754 floating-point representation, each number comprises three basic components: the sign, the exponent, and the mantissa. To maximize the range of possible numbers, the mantissa is divided into a fraction and leading digit. As I'll explain, the latter is implicit and left out of the representation.

The sign bit simply defines the polarity of the number. A value of zero means that the number is positive, whereas a 1 denotes a negative number.

The exponent represents a range of numbers, positive and negative; thus a bias value must be subtracted from the stored exponent to yield the actual exponent. The single precision bias is 127, and the double precision bias is 1,023. This means that a stored value of 100 indicates a single-precision exponent of -27. The exponent base is always 2, and this implicit value is not stored.

For both representations, exponent representations of all 0s and all 1s are reserved and indicate special numbers:

Zero: all digits set to 0, sign bit can be either 0 or 1
±∞: exponent all 1s, fraction all 0s
Not a Number (NaN): exponent all 1s, non-zero fraction. Two versions of NaN are used to signal the result of invalid operations such as dividing by zero, and indeterminate results such as operations with non-initialized operand(s).

The mantissa represents the number to be multiplied by 2 raised to the power of the exponent. Numbers are always normalized; that is, represented with one non-zero leading digit in front of the radix point. In binary math, there is only one non-zero number, 1. Thus the leading digit is always 1, allowing us to leave it out and use all the mantissa bits to represent the fraction (the decimals).

Following the previous number examples, here is what the single precision representation of the decimal value 30,064,771 will look like:

The binary integer representation of 30,064,771 is 1 1100 1010 1100 0000 1000 0011. This can be written as 1.110010101100000010000011 x 2²⁴. The leading digit is omitted, and the fraction—the string of digits following the radix point—is 1100 1010 1100 0000 1000 0011. The sign is positive and the exponent is 24 decimal. Adding the bias of 127 and converting to binary yields an IEEE 754 exponent of 1001 0111.

Putting all of the pieces together, the single representation for 30,064,771 is shown in Figure 3.

Figure 3: 30,064,771 represented in IEEE 754 single-precision format

Gain Some, Lose Some
Notice that you lose the least significant bit (LSB) of value 1 from the 32-bit integer representation—this is because of the limited precision for this format.

The range of numbers that can be represented with single precision IEEE 754 representation is ±(2-2^-23) x 2¹²⁷, or approximately ±10^38.53. This range is astronomical compared to the maximum range of 32-bit integer numbers, which by comparison is limited to around ±2.15 x 10⁹. Also, whereas the integer representation cannot represent values between 0 and 1, single-precision floating-point can represent values down to ±2^-149, or ±~10^-44.85. And we are still using only 32 bits—so this has to be a much more convenient way to represent numbers, right?

The answer depends on the requirements.

Yes, because in our example of multiplying 30,064,771 by 1.001, we can simply multiply the two numbers and the result will be extremely accurate.
No, because as in the preceding example the number 30,064,771 is not represented with full precision. In fact, 30,064,771 and 30,064,770 are represented by the exact same 32-bit bit pattern, meaning that a software algorithm will treat the numbers as identical. Worse yet, if you increment either number by 1 a billion times, none of them will change. By using 64 bits and representing the numbers in double precision format, that particular example could be made to work, but even double-precision representation will face the same limitations once the numbers get big—or small enough.
No, because most embedded processor cores ALUs (arithmetic logic units) only support integer operations, which leaves floating-point operations to be emulated in software. This severely affects processor performance. A 32-bit CPU can add two 32-bit integers with one machine code instruction; however, a library routine including bit manipulations and multiple arithmetic operations is needed to add two IEEE single-precision floating-point values. With multiplication and division, the performance gap just increases; thus for many applications, software floating-point emulation is not practical.

Keywords: IEEE 754, Floating point representaion

Memory Types

2006-12-12T21:24:00.000-08:00

There are several different technologies when it comes to memory.

ROM

This is read-only memory, memory that can only be read, but cannot be written to. ROM is used in situations where the data must be held permanently. This is due to the fact that it is non-volatile memory. This means the data is "hard-wired" into the ROM chip.You can store the chip forever and the data will always be there. Besides, the data is very secure. The BIOS is stored on ROM because the user cannot disrupt the information.

There are different types of ROM, too:

Programmable ROM(PROM). This is basically a blank ROM chip that can be written to, but only once. It is much like a CD-R drive that burns the data into the CD. Some companies use special machinery to write PROMs for special purposes.
Erasable Programmable ROM (EPROM). This is just like PROM, except that you can erase the ROM by shining a special ultra-violet light into a sensor atop the ROM chip for a certain amount of time. Doing this wipes the data out, allowing it to be rewritten.
Electrically Erasable Programmable ROM (EEPROM). Also called flash BIOS. This ROM can be rewritten through the use of a special software program. Flash BIOS operates this way, allowing users to upgrade their BIOS.

ROM is slower than RAM, which is why some try to shadow it to increase speed.

RAM
Random Access Memory (RAM) is what most of us think of when we hear the word memory associated with computer. It is volatile memory, meaning all data is lost when power is turned off. The RAM is used for temporary storage of program data, allowing performance to be optimum.

Like ROM, there are different types of RAM:

Static RAM (SRAM) This RAM will maintain it's data as long as power is provided to the memory chips. It does not need to be re-written periodically. In fact, the only time the data on the memory is refreshed or changed is when an actual write command is executed. SRAM is very fast, but is much more expensive than DRAM. SRAM is often used as cache memory due to its speed.
There are a few types of SRAM:

Async SRAM. An older type of SRAM used in many PC's for L2 cache. It is asynchronous, meaning that it works independently of the system clock. This means that the CPU found itself waiting for info from the L2 cache.
Sync SRAM. This type of SRAM is synchronous, meaning it is synchronized with the system clock. While this speeds it up, it makes it rather expensive at the same time.
Pipeline Burst SRAM. Commonly used. SRAM requests are pipelined, meaning larger packets of data re sent to the memory at once, and acted on very quickly. This breed of SRAM can operate at bus speeds higher than 66MHz, so is often used.

Dynamic RAM (DRAM). DRAM, unlike SRAM, must be continually re-written in order for it to maintain its data. This is done by placing the memory on a refresh circuit that re-writes the data several hundred time per second. DRAM is used for most system memory because it is cheap and small.
There are several types of DRAM, complicating the memory scene even more:

Fast Page Mode DRAM (FPM DRAM). FPM DRAM is only slightly faster than regular DRAM. Before there was EDO RAM, FPM RAM was the main type used in PC's. It is pretty slow stuff, with an access time of 120 ns. It was eventually tweaked to 60 ns, but FPM was still too slow to work on the 66MHz system bus. For this reason, FPM RAM was replaced by EDO RAM. FPM RAM is not much used today due to its slow speed, but is almost universally supported.
Extended Data Out DRAM (EDO DRAM). EDO memory incorporates yet another tweak in the method of access. It allows one access to begin while another is being completed. While this might sound ingenious, the performance increase over FPM DRAM is only around 30%. EDO DRAM must be properly supported by the chipset. EDO RAM comes on a SIMM. EDO RAM cannot operate on a bus speed faster than 66MHz, so, with the increasing use of higher bus speeds, EDO RAM has taken the path of FPM RAM.
Burst EDO DRAM (BEDO DRAM). Original EDO RAM was too slow for the newer systems coming out at the time. Therefore, a new method of memory access had to be developed to speed up the memory. Bursting was the method devised. This means that larger blocks of data were sent to the memory at a time, and each "block" of data not only carried the memory address of the immediate page, but info on the next several pages. Therefore, the next few accesses would not experience any delays due to the preceding memory requests. This technology increases EDO RAM speed up to around 10 ns, but it did not give it the ability to operate stably at bus speeds over 66MHz. BEDO RAM was an effort to make EDO RAM compete with SDRAM.
Synchronous DRAM (SDRAM). SDRAM became the new standard after EDO bit the dust. Its speed is synchronous, meaning that it is directly dependent on the clock speed of the entire system. Standard SDRAM can handle higher bus speeds. In theory, it could operate at up to 100MHz, although it was found that many other variable factors went into whether or not it could stabily do so. The actual speed capacity of the module depended on the actual memory chips as well as design factors in the memory PCB itself.

Do get around the variability, Intel created the PC100 standard. The PC100 standard ensures compatibility of SDRAM subsystems with Intel's 100MHz FSB processors. The new design, production, and test requirements created challenges for semiconductor companies and memory module suppliers. Each PC100 SDRAM module required key attributes to guarantee full compliance, such as the use of 8ns DRAM components (chips) that are capable of operating at 125MHz. This provided a margin of safety in ensuring that that the memory module could run at PC100 speeds. Additionally, SDRAM chips must be used in conjunction with a correctly programmed EEPROM on a properly designed printed circuit board. The shorter the distance the signal needs to travel, the faster it runs. For this reason, there were additional layers of internal circuitry on PC100 modules.

As PC speeds increased, the same problem was encountered for the 133 MHz bus, so the PC133 standard was developed.
RAMBus DRAM (RDRAM). Developed by Rambus, Inc. and endorsed by Intel as the chosen successor to SDRAM. RDRAM narrows the memory bus to 16-bit and runs at up to 800 MHz. Since this narrow bus takes up less space on the board, systems can get more speed by running multiple channels in parallel. Despite the speed, RDRAM has had a tough time taking off in the market because of compatibility and timing issues. Heat is also an issue, but RDRAM has heatsinks to dissipate this. Cost is a major issue with RDRAM, with manufacturers needing to make major facility changes to make it and the product cost to consumers being too high for people to swallow.
DDR-SDRAM. This type of memory is the natural evolution from SDRAM and most manufacturers prefer this to Rambus because not much needs to be changed to make it. Also, memory makers are free to manufacture it because it is an open standard, whereas they would have to pay license fees to Rambus, Inc. in order make RDRAM. DDR stands for Double Data Rate. DDR shuffles data over the bus over both the rise and fall of the clock cycle, effectively doubling the speed over that of standard SDRAM. Of course, chipset support is necessary. DDR-DRAM is now the new standard in PC memory, with ever increasing speed support coming out, even so that it can compete quite well up against Rambus.
Ref: http://www.pcmech.com/show/memory/110/

Keywords: Memory, SSRAM, DDR SDRAM, Rambus,